<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
  <head>
    <title>TRCIDR2</title>
    <link href="insn.css" rel="stylesheet" type="text/css"/>
  </head>
  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">TRCIDR2, ID Register 2</h1><p>The TRCIDR2 characteristics are:</p><h2>Purpose</h2>
        <p>Returns the tracing capabilities of the trace unit.</p>
      <h2>Configuration</h2><p>AArch64 System register TRCIDR2 bits [31:0] are architecturally mapped to External register <a href="ext-trcidr2.html">TRCIDR2[31:0]</a>.</p><p>This register is present only when FEAT_ETE is implemented and FEAT_TRC_SR is implemented. Otherwise, direct accesses to TRCIDR2 are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>TRCIDR2 is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_32">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_31">WFXMODE</a></td><td class="lr" colspan="2"><a href="#fieldset_0-30_29">VMIDOPT</a></td><td class="lr" colspan="4"><a href="#fieldset_0-28_25-1">CCSIZE</a></td><td class="lr" colspan="5"><a href="#fieldset_0-24_20-1">DVSIZE</a></td><td class="lr" colspan="5"><a href="#fieldset_0-19_15-1">DASIZE</a></td><td class="lr" colspan="5"><a href="#fieldset_0-14_10">VMIDSIZE</a></td><td class="lr" colspan="5"><a href="#fieldset_0-9_5">CIDSIZE</a></td><td class="lr" colspan="5"><a href="#fieldset_0-4_0">IASIZE</a></td></tr></tbody></table><h4 id="fieldset_0-63_32">Bits [63:32]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-31_31">WFXMODE, bit [31]</h4><div class="field">
      <p>Indicates whether <span class="instruction">WFI</span>, <span class="instruction">WFIT</span>, <span class="instruction">WFE</span>, and <span class="instruction">WFET</span> instructions are classified as P0 instructions:</p>
    <table class="valuetable"><tr><th>WFXMODE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><span class="instruction">WFI</span>, <span class="instruction">WFIT</span>, <span class="instruction">WFE</span>, and <span class="instruction">WFET</span> instructions are not classified as P0 instructions.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><span class="instruction">WFI</span>, <span class="instruction">WFIT</span>, <span class="instruction">WFE</span>, and <span class="instruction">WFET</span> instructions are classified as P0 instructions.</p>
        </td></tr></table></div><h4 id="fieldset_0-30_29">VMIDOPT, bits [30:29]</h4><div class="field">
      <p>Indicates the options for Virtual context identifier selection.</p>
    <table class="valuetable"><tr><th>VMIDOPT</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Virtual context identifier selection not supported. <a href="AArch64-trcconfigr.html">TRCCONFIGR</a>.VMIDOPT is <span class="arm-defined-word">RES0</span>.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td>
          <p>Virtual context identifier selection supported. <a href="AArch64-trcconfigr.html">TRCCONFIGR</a>.VMIDOPT is implemented.</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>Virtual context identifier selection not supported. <a href="AArch64-trcconfigr.html">TRCCONFIGR</a>.VMIDOPT is <span class="arm-defined-word">RES1</span>.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>If TRCIDR2.VMIDSIZE == <span class="binarynumber">0b00000</span> then this field is <span class="binarynumber">0b00</span>.</p>
<p>If TRCIDR2.VMIDSIZE != <span class="binarynumber">0b00000</span> then this field is <span class="binarynumber">0b10</span>.</p></div><h4 id="fieldset_0-28_25-1">CCSIZE, bits [28:25]<span class="condition"><br/>When TRCIDR0.TRCCCI == 1:
                        </span></h4><div class="field">
      <p>Indicates the size of the cycle counter.</p>
    <table class="valuetable"><tr><th>CCSIZE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>The cycle counter is 12 bits in length.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>The cycle counter is 13 bits in length.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>The cycle counter is 14 bits in length.</p>
        </td></tr><tr><td class="bitfield">0b0011</td><td>
          <p>The cycle counter is 15 bits in length.</p>
        </td></tr><tr><td class="bitfield">0b0100</td><td>
          <p>The cycle counter is 16 bits in length.</p>
        </td></tr><tr><td class="bitfield">0b0101</td><td>
          <p>The cycle counter is 17 bits in length.</p>
        </td></tr><tr><td class="bitfield">0b0110</td><td>
          <p>The cycle counter is 18 bits in length.</p>
        </td></tr><tr><td class="bitfield">0b0111</td><td>
          <p>The cycle counter is 19 bits in length.</p>
        </td></tr><tr><td class="bitfield">0b1000</td><td>
          <p>The cycle counter is 20 bits in length.</p>
        </td></tr></table>
      <p>All other values are reserved.</p>
    </div><h4 id="fieldset_0-28_25-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-24_20-1">DVSIZE, bits [24:20]<span class="condition"><br/>When TRCIDR0.TRCDATA != 0b00:
                        </span></h4><div class="field">
      <p>Indicates the data value size in bytes. Data tracing is not implemented in ETE and this field is reserved for other trace architectures. Allocated in other trace architectures.</p>
    <table class="valuetable"><tr><th>DVSIZE</th><th>Meaning</th></tr><tr><td class="bitfield">0b00000</td><td>
          <p>Data value tracing not implemented.</p>
        </td></tr><tr><td class="bitfield">0b00100</td><td>
          <p>Data value tracing has a maximum of 32-bit data values.</p>
        </td></tr><tr><td class="bitfield">0b01000</td><td>
          <p>Data value tracing has a maximum of 64-bit data values.</p>
        </td></tr></table>
      <p>All other values are reserved.</p>
    </div><h4 id="fieldset_0-24_20-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-19_15-1">DASIZE, bits [19:15]<span class="condition"><br/>When TRCIDR0.TRCDATA != 0b00:
                        </span></h4><div class="field">
      <p>Indicates the data address size in bytes. Data tracing is not implemented in ETE and this field is reserved for other trace architectures. Allocated in other trace architectures.</p>
    <table class="valuetable"><tr><th>DASIZE</th><th>Meaning</th></tr><tr><td class="bitfield">0b00000</td><td>
          <p>Data address tracing not implemented.</p>
        </td></tr><tr><td class="bitfield">0b00100</td><td>
          <p>Data address tracing has a maximum of 32-bit data addresses.</p>
        </td></tr><tr><td class="bitfield">0b01000</td><td>
          <p>Data address tracing has a maximum of 64-bit data addresses.</p>
        </td></tr></table>
      <p>All other values are reserved.</p>
    </div><h4 id="fieldset_0-19_15-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-14_10">VMIDSIZE, bits [14:10]</h4><div class="field">
      <p>Indicates the trace unit Virtual context identifier size.</p>
    <table class="valuetable"><tr><th>VMIDSIZE</th><th>Meaning</th></tr><tr><td class="bitfield">0b00000</td><td>
          <p>Virtual context identifier tracing is not supported.</p>
        </td></tr><tr><td class="bitfield">0b00001</td><td>
          <p>8-bit Virtual context identifier size.</p>
        </td></tr><tr><td class="bitfield">0b00010</td><td>
          <p>16-bit Virtual context identifier size.</p>
        </td></tr><tr><td class="bitfield">0b00100</td><td>
          <p>32-bit Virtual context identifier size.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>If the PE does not implement EL2 then this field is <span class="binarynumber">0b00000</span>.</p>
<p>If the PE implements EL2 then this field is <span class="binarynumber">0b00100</span>.</p></div><h4 id="fieldset_0-9_5">CIDSIZE, bits [9:5]</h4><div class="field">
      <p>Indicates the Context identifier size.</p>
    <table class="valuetable"><tr><th>CIDSIZE</th><th>Meaning</th></tr><tr><td class="bitfield">0b00000</td><td>
          <p>Context identifier tracing is not supported.</p>
        </td></tr><tr><td class="bitfield">0b00100</td><td>
          <p>32-bit Context identifier size.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>This field reads as <span class="binarynumber">0b00100</span>.</p></div><h4 id="fieldset_0-4_0">IASIZE, bits [4:0]</h4><div class="field">
      <p>Virtual instruction address size.</p>
    <table class="valuetable"><tr><th>IASIZE</th><th>Meaning</th></tr><tr><td class="bitfield">0b00100</td><td>
          <p>Maximum of 32-bit instruction address size.</p>
        </td></tr><tr><td class="bitfield">0b01000</td><td>
          <p>Maximum of 64-bit instruction address size.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>This field reads as <span class="binarynumber">0b01000</span>.</p></div><div class="access_mechanisms"><h2>Accessing TRCIDR2</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRS &lt;Xt&gt;, TRCIDR2</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b10</td><td>0b001</td><td>0b0000</td><td>0b1010</td><td>0b111</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; CPTR_EL3.TTA == '1' then
        UNDEFINED;
    elsif CPACR_EL1.TTA == '1' then
        AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() &amp;&amp; CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') &amp;&amp; HDFGRTR_EL2.TRCID == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; CPTR_EL3.TTA == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif IsFeatureImplemented(FEAT_TRBE_EXT) &amp;&amp; OSLSR_EL1.OSLK == '0' &amp;&amp; HaltingAllowed() &amp;&amp; EDSCR2.TTA == '1' then
        Halt(DebugHalt_SoftwareAccess);
    else
        X[t, 64] = TRCIDR2;
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; CPTR_EL3.TTA == '1' then
        UNDEFINED;
    elsif CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; CPTR_EL3.TTA == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif !ELUsingAArch32(EL1) &amp;&amp; IsFeatureImplemented(FEAT_TRBE_EXT) &amp;&amp; OSLSR_EL1.OSLK == '0' &amp;&amp; HaltingAllowed() &amp;&amp; EDSCR2.TTA == '1' then
        Halt(DebugHalt_SoftwareAccess);
    else
        X[t, 64] = TRCIDR2;
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif !ELUsingAArch32(EL1) &amp;&amp; IsFeatureImplemented(FEAT_TRBE_EXT) &amp;&amp; OSLSR_EL1.OSLK == '0' &amp;&amp; HaltingAllowed() &amp;&amp; EDSCR2.TTA == '1' then
        Halt(DebugHalt_SoftwareAccess);
    else
        X[t, 64] = TRCIDR2;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
</html>
